Transactional Memory

Outline

• Introduction
• Hardware Transactional Memory
• Intel TSX
• Others
• Software Transactional Memory
• TinySTM
• RSTM
• Compilers
• Benchmarks
• STAMP
• Others

Introduction

Transactional Memory is new synchronization mechanism proposed as an alternative for locks. The main purpose is to make easier the concurrent programming.

Hardware Transactional Memory

Intel Transactional Synchronization Extensions (TSX)

Intel TSX is a new instructions set for Hardware Restricted Transactional Memory (RTM) and Hardware Lock Elision (HLE). It will be integrated with the next generation processor named Haswell in March-June 2013. The full specification can be found inside the new AVX Intel Architecture Instruction Set Extensions Programming Reference (also named 319433-012). Note: Restricted seems to mean that in the future the instructions set (ISA) will evolve to provide unrestricted HTM. Information about the implementation are not published yet.

How to use Intel TSX?

In Linux, binutils 2.22.52+ (particularly gas, GNU assembler) already supports the new instructions so it makes really to use them. Nasm 2.10 also supports TSX instructions. GCC 4.8 will also support RTM and HLE via builtins (already available in the development branch of GCC).

Here some macros you can use Intel TSX/RTM.

IBM BlueGene/Q

IBM has released HTM in the Blue Gene/Q processor but it seems that no documentation is available about it yet.

AMD Advanced Synchronization Facility (ASF)

ASF is an experimental AMD64 extension that allows user- and system-level code to modify a set of memory objects atomically without requiring expensive synchronization mechanisms. Unfortunately, no hardware is available so ASF is implemented into a version of the open-source AMD64 simulator PTLsim. link

Sun Rock

Sun Rock was a multicore SPARC processor with Hardware Transactional Memory. While the commercial product was cancelled, some researchers had access to some Rock prototype as they published some results ("Early experience with a commercial hardware transactional memory implementation", "The Adaptive Transactional Memory Test Platform: A tool for experimenting with transactional code for Rock", "NZTM: Nonblocking zero-indirection transactional memory", "Simplifying concurrent algorithms by exploiting hardware transactional memory"). However, it seems that Oracle will include memory versioning (ie TM) in future SPARC processors.

Software Transactional Memory

TinySTM

link

RSTM

RSTM (Rochester Software Transactional Memory). link

Compilers

GCC 4.7 implements an experimental Transactional Memory support.

Benchmarks

STAMP